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翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク Extendable instruction set computer ： ウィキペディア英語版 Extendable instruction set computer The EISC (Extendable Instruction Set Computer) is a compressed code processor architecture for embedded applications. It has both the properties of RISC architecture, simplicity, and that of CISC processor, expandability. The architecture is developed by Advanced Digital Chips Inc., Seoul, Korea. ==EISC core Introduction== ::Introduction ::EISC stands for"Extendable Instruction Set Computer.", EISC processor advantages over existing CISC and RISC architectures. EISC can represent any length of an operand without variable length instruction elimination inefficiencies caused by difficulties in processing variable instruction decoding. EISC architecture maximized cost / performance efficiency and at the same time offers flexibility and power through the Extendable Register and Extension Flag, which increase the code density while allowing a simple 16 bit based instruction set. ::(EISC ISA link ) 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Extendable instruction set computer」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.